Resume Hans de Vries


 by Hans de Vries 



    2007-2009:    Graduate University textbook on Relativistic Quantum Field Fheory
Some parts of my graduate text book (in progress) are available online:  click on the logo   
      Understanding Relativistic Quantum Field Theory
Part    I
Part   II
Part  III
Part  IV
Part   V
Relativistic foundations of light and matter Fields
Advanced treatment of the EM field
The relativistic matter wave equations
Foundations of Quantum Electro Dynamics
Non Abelian gauge theories

New opportunities in  high performance technical data processing require increasing levels of advanced physics in application area's as Medical scanning and visualization, Molecular modeling , Computational Biotechnology.  Advances in FPGA numerical megacells and of the shelf GPGPU's allow for a lower entrance level as tradition ASIC based solutions.

     2001-2006:    Third generation GPGPU stream processor:   GenTera  MT3  -  Imagine 3


I had the lead architect reponsibility for the MT3.
A third generation GPGPU processor integrating
Streaming SIMD Floating Point  cores
Open GL compatible
3D graphics pipelines with
numerous medical volume rendering extensions,

 Fully integrated Video I/O, Audio I/O and legacy IO
- First silicon was achieved in 2006 -
Click on the images for some presentations:

MT3 overview


HISC pyramid


      2001-2006 Derivatives of Imagine I     

Numerous companies use derivatives of the original Imagine processor
which was designed by me as the Lead Architect.
One of the latest incarnations is the XTrillion 3.0

- The XTrillion 3.0  is an 8 Core multiprocessor for Medical Applications -

XTrillion 3.0

     1996 - 2000    Second generation GPGPU stream processor:   Arcobel Graphics / GenTera  Imagine 2



The MT2 was our second generation GPGPU processor .
It had a full hardware implementations of Open GL compatible 3D graphics pipelines.
Advanced Floating point  support was added throughout the architecture.
including fully pipelined 32 bit Floating Point Transcendental functions.



3D Graphics Pipeline


Advanced Floating Point units


     1991-1995    Arcobel Graphics  - Imagine 1:    Worlds First single chip GPGPU stream processor

At Arcobel Graphics I was responsible
for the design of the Imagine 1 graphics and Image processor.


- It was the fastest 3D graphics processor on the market when it was released. -

It could both function as a stream processor as well as a
RISC processor executing C code

Imagine 1 - graphics and image processor

Imagine 1 graphics and image processor
1987-1990     DTN:   3D Graphics and Image processing Systollic Array board  


At Dataflow Technology I designed the 3D graphics and
Image processing systolic array board.
The product line was purchased and marketed by Radstone

---Radstone Vision Master Hans de Vries---

It had a camara input which we used to capture the public during presentations
to show them live texture mapped on moving and rotating 3D graphics objects.
Up to four boards, each with 4 PCB's could cooperate as a multiprocessing system
with a shared graphics memory of up tp 64 Megabytes which was very
large those days, consisting out of 1024 DRAM and VRAM chips

3D graphics and Image processing board


     1987-1990     DTN:   Dataflow processor  



The company DTN was a management buy out from Philips and I had the

responsibility for design of the "fifth generation" dataflow computer. 


The company was partly funded by governments grants. 

Fifth generation computers were a very hot item these days. 

There was for the first time a notion that  computers would become

large massively parallel processing engines.


Many often radically different architectures were considered to harness 

all the processing power which would become available.

The general expectation was that progress would come from applying new 

programming languages, advanced compilers, new computer architectures

together with inter connection systems.


DTN dataflow computer



  Article about the DTN Dataflow Computer in Dutch



The RC compiler for the DTN dataflow computer

Journal of Parallel and Distributed Computing
Volume 10, Issue 4,   December 1990, Pages 319-332

Arthur H. Veen and Reinier Van Den Born

Parallel Computing, Postbus 16775, 1001, RG Amsterdam, The Netherlands


The DTN Dataflow Computer is a graphics workstation containing 32 dataflow processing elements. It may possibly be the first commercially available dataflow machine. In this article our main focus is on its RC compiler. Although dataflow machines are usually programmed in a declarative language, RC is imperative: it is a somewhat restricted form of C. 



Regards, Hans








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