June 23, 2000: News on Willamette cache organisation
An early memory benchmark (cachemem2.2) might
reveal some of Willamette's internal cache organization:
The 8 kByte size for the L1 data cache follows
from the decrease in read bandwidth at block sizes larger then 8kByte (We
don't know actually how cachemem arrives at these numbers). The 4
way set-associativity was already disclosed by Intel. The 256 kByte is
a known number from OEM presentatons.The benchmark shows an unexplained
bandwidth decrease at the 128 kByte level. The L1 data cache is operating
in a Write-Thru mode: All writes to the L1 data cache are also written
to the L2 cache. This means that the L2 cache is "Inclusive":
All L1 cache-lines are also found in the L2 cache.
Willamette meets Pikachu The 800 MHz Willamette system seems to come from
an early system integrator (Which should be possible considering the planed
October launch) It was exposed to the web by a young guy nicknamed
"Pikachu"
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